Advanced Platform Architecture Package Vista™ Architect is a complete TLM 2.0-based solution for architecture design and exploration enable system architects and SoC designers to make viable architecture decisions, prototype and analyze complex systems, understand the key scaling algorithms, and ensure optimized architecture, shorter implementation cycle and first time success. View Detail As, networking, storage systems and multi-core SoCs are rapidly becoming more complex, making architecture decisions increasingly critical and directly impacting competitive advantage. Configuring multi-core hardware/software architectures and communication fabrics, and ensuring the system can carry its load and data traffic capacities, are all critical tasks. Vista Architect offers top-down modeling (Vista Model Builder), a set of key architecture blocks that can be easily configured, an intuitive graphical assembly platform (Visual Elite SD), and hardware/software debug and analysis toolset. The models constructing the system can be intuitively set to various micro-architecture configurations, interconnect layering and memory hierarchies. The unique layered timing approach offered by Vista Architect enables users to quickly test the various configurations using powerful timing policies while keeping functionality intact. Users can scale and tune timing and power accuracy from high-level approximation down to the target bus and protocol. For efficient data tracing, users can utilize complex data objects (data packets), tag them with an “ID” then trace and analyze their flow in the system. Users can exercise statistical and randomized data traffic simulation or SW-driven simulation with a target processor. Vista Architect has a powerful analysis toolset that allows a user to intuitively view and analyze different performance and power metrics, look at load peaks, average latencies, throughput and utilization on any port, bus or sub-system. With Vista Architect users can rapidly prototype systems with the key hardware blocks and analyze power and performance under different scenarios and traffic loads. The scalable modeling approach supported in Vista enables design teams to manage timing and power from system concept down to the desired implementation ensuring silicon is optimized, can carry the data capacities for a given application and is scalable to support future derivation of the product. The users are also offered with all the validation and debugging features available with Vista Design. Features and Benefits Benefits Early assessment of performance and power metrics Minimizes risks and maximizes quality of results Manage and balance timing and power budgets from concept to implementation Understand the properties of the key scaling algorithms Allow deterministic scalability Features Set of configurable TLM 2.0-based architecture blocks CPU, BUS (AXI, AHB), Memory, Cache, DMAC, INTC, and others Statistical and functional up-front Modeling utilities Tracing of data packets and model states and attributes TLM 2.0 Graphical Assembly with Visual Elite Integrated HW/SW platform with target processors and SW tools Advanced SystemC and TLM 2.0 debug and tracing Advanced analysis and visualization tools and reports Analyze power, throughput, latencies, utilization, and states